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| TECHNICAL DATA IN74LV86 Quad 2-Input Exclusive OR Gate The 74LV86 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT86. The 74LV86 provides the 2-input EXCLUSIVE-OR function. * Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS * Supply voltage range: 1.2 to 5.5 V * Low input current: 1.0 ; 0.1 at = 25 * Output current: 6 mA at Vcc = 3.0 V; 12 mA at Vcc = 4.5V * High Noise Immunity Characteristic of CMOS Devices N SUFFIX PLASTIC 14 1 14 D SUFFIX SOIC 1 ORDERING INFORMATION IN74LV86N Plastic IN74LV86D SOIC TA = -40 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs PIN 16=VCC PIN 08 = GND An L L H H H= high level L = low level Bn H L L H Outputs Yn H L H L 1 IN74LV86 MAXIMUM RATINGS* Symbol VCC IIK * IO * ICC IGND PD 1 2 Parameter DC supply voltage Input diode current Output diode current Output source or sink current VCC current GND current Power dissipation per package: * Plastic DIP SO Storage Temperature Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds 4 Value -0.5 to +5.0 20 50 25 50 50 750 500 -65 to +150 260 Unit V mA mA mA mA mA mW IOK * 3 Tstg TL * C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. *1 VI < -0.5 V or VI > VCC + 0.5 V. *2 VO < -0.5 V or VO > VCC + 0.5 V. *3 -0.5 V < VO < VCC + 0.5 V. *4 Derating - Plastic DIP: - 12 mW/C from 70 to 125C SO Package: : - 8 mW/C from 70 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO TA tr, tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) 1.0 VCC <2.0 2.0 VCC <2.7 2.7 VCC <3.6 3.6 VCC 5.5 Parameter Min 1.2 0 0 -40 0 0 0 0 Max 5.5 VCC VCC +125 500 200 100 50 Unit V V V C ns/V This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IN74LV86 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Test Symbol VIH Parameter HIGH level input voltage conditions VCC V 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 VI = VIH or VIL IO = -100 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 4.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 4.5 5.5 5.5 2.7 3.6 -40C to 25C min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.05 1.85 2.55 2.85 3.45 4.35 5.35 2.48 3.70 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.33 0.40 0.1 4.0 0.2 0.2 Guaranteed Limit 85C min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.34 3.60 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.40 0.55 1.0 20 0.5 0.5 125C min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.20 3.50 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.50 0.65 1.0 40 0.85 0.85 V Unit VIL LOW level input voltage V VOH HIGH level output voltage V VI = VIH or VIL IO = -6 m VI = VIH or VIL IO = -12 m VOL LOW level output voltage VI = VIH or VIL IO = 100 V V V VI = VIH or VIL IO = 6 m VI = VIH or VIL IO = 12 m II ICC ICC1 Input current Supply current Additional quiescent supply current per input VI = VCC or 0 V VI =VCC or 0 V IO = 0 VI =VCC - 0.6 V V V mA 3 IN74LV86 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, RL = 1 k, tr=tf=2.5 ns) Test Symbol Parameter conditions VI = 0 V or VCC Figure 1, 2 VCC V 1.2 2.0 2.7 3.0 4.5 5.0 5.5 min tPHL, tPLH Propagation delay , An ,Bn, to Yn Guaranteed Limit -40C to 25C max 140 24 19 15 13 7.0 60 85C min max 150 32 24 19 16 125C min max 180 41 30 24 20 ns Unit CI CPD Input capacitance Power dissipation capacitance (per gate) A = 25C VI = 0 V or VCC TA = 25C pF pF tr INPUT A OR B 90% 10% VM (1) tf V1 (2) GND t PHL VOH VOL t PLH OUTPUT Y VM (1) Figure 1. Switching Waveforms Note: (1) (2) VM = 1.5 V at VCC = 2.7 V VM = 0.5 VCC at VCC =1.2 V, 2.0 V, 3.0 V, 4.5 V V1 = VCC at VCC =1.2 V, 2.0 V, 2.7 V, 4.5 V V1 = 2.7 V at VCC = 3.0 V TEST POINT DEVICE UNDER TEST OUTPUT RL CL * * Includes all probe and jig capacitance Figure 4. Test Circuit 4 IN74LV86 N SUFFIX PLASTIC DIP (MS - 001AA) A 14 8 B 1 7 Dimension, mm Symbol A B C MIN 18.67 6.1 MAX 19.69 7.11 5.33 0.36 1.14 2.54 7.62 0 2.92 7.62 0.2 0.38 10 3.81 8.26 0.36 0.56 1.78 F L D F C -T- SEATING N G D 0.25 (0.010) M T K PLANE G H H J M J K L M N NOTES: 1. Dimensions "A", "B" do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D SUFFIX SOIC (MS - 012AB) Dimension, mm 8 A 14 Symbol A MIN 8.55 3.8 1.35 0.33 0.4 1.27 5.27 0 0.1 0.19 5.8 0.25 MAX 8.75 4 1.75 0.51 1.27 H B P B C 1 G 7 C R x 45 D F G -TD 0.25 (0.010) M T C M K SEATING PLANE H J F M J K M P R 8 0.25 0.25 6.2 0.5 NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B 0.25 mm (0.010) per side. 5 |
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